1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices and, more particularly, to a semiconductor memory device having an internal power supply circuit such as a dynamic random access memory (hereinafter referred to as a DRAM).
2. Description of the Background Art
As the result of scaling down a gate length of an MOS transistor in accordance with a larger scale integration of a semiconductor memory device such as a DRAM, it is effective to lower an operating supply voltage in order to achieve reliability of transistors and also decrease power consumption thereof. However, a conventional voltage of 5 V must be applied as an external voltage level of semiconductor memory devices in order to maintain compatibility with transistor logic (hereinafter referred to as TTL).
Thus, a method is adopted in general in which an internal voltage down converter for lowering an external power supply voltage ext. V.sub.CC from 5 V to approximately 3 V to 4 V to apply the lowered voltage to an internal circuit is formed in a chip, so as to satisfy a higher reliability, a faster operation and a lower power consumption.
Further, despite an exponential decrease of a memory cell area due to the larger scale integration of the DRAM, a capacitance of a memory cell capacitor must be a definite value or above in order to maintain a sufficient immunity to soft errors, namely sufficient S/N ratios, thereby inevitably leading to a thinner insulator film of the memory cell capacitor. The smaller thickness of the film causes, however, some difficulties such as a degradation in film quality and an increase of tunnel currents. In order to decrease such difficulties, such a method is generally adopted that a memory cell plate potential V.sub.CF is set to V.sub.CC /2 so as to decrease an electric field strength in the insulator film.
Moreover, larger scale integration leads to a very small spacing between bit lines, and interference noises which come from adjacent bit lines through coupling capacitance between the bit lines cannot be neglected. As a countermeasure to such interference noises, bit line pairs are adjacently disposed so as to superimpose noises on the bit line pairs in common and cancel the noises. In this case, the potential of the bit lines are set to a potential of V.sub.CC /2 (a precharge voltage: V.sub.BL) in a standby period.
Further, in order to attain a faster operation of circuits by reducing a capacitance of a p-n junction formed between an n.sup.+ contact region of an n channel MOS transistor and a p well having the n.sup.+ region formed therein, for example, a negative voltage V.sub.BB of approximately -2 V to -3 V is generally applied to the p well or a p type silicon substrate itself. This negative voltage is also generated by a substrate biasing circuit formed on a chip from a 5 V single power supply.
As described above, such semiconductor memory devices as DRAMs having larger scale integration incorporate therein internal power supplies in which various potentials necessary for their circuit operation are formed within chips even if an external power supply is a 5 V single power supply.
These internal power supply circuits are designed to have circuit configurations in which generated potentials are hardly affected by process variations or the like. Therefore, while those internal power supply potentials are held at designed values in a steady state, the potentials are varied by various factors during the actual operation of the semiconductor memory devices.
In memory cell circuits for storing memory, sense amplifier circuits for carrying out a reading operation, and the like which are driven by those internal power supplies, ranges in which those circuits are normally operable (operating margins) are also varied for internal power supply potentials due to external factors such as process variations.
Thus, testing variations of characteristics of the internal circuits of DRAMs, which occur with dispersion of internal power supply voltages leads to exact evaluations of operating margins, resulting in a higher reliability of DRAMs as systems formed of those internal circuits.
FIG. 12 is a schematic block diagram showing a configuration of a conventional DRAM. With reference to FIG. 12, an address buffer 105 selectively applies externally applied address signals A0-A8 to a row decoder 102 and a column decoder 103. Row decoder 102 selects one of a plurality of word lines WL to drive the selected one in response to a row address signal applied from address buffer 105. Column decoder 103 selects one of a plurality of bit line pairs in response to a column address signal applied from address buffer 105.
A sense amplifier 104 amplifies potential differences between their corresponding bit line pairs. An amplified signal corresponding to the bit line pair selected by column decoder 103 is applied to an output buffer 107. Output buffer 107 amplifies its applied potential and outputs the amplified potential as output data DQ1-DQ8. A data input buffer 106 amplifies externally applied input data DQ1-DQ8. The amplified signal is applied to the bit line pair selected by column decoder 103.
A description will be given on a reading operation of the conventional DRAM shown in the schematic block diagram of FIG. 12 by reference to FIG. 13 of a timing chart of external signals. At a time point at which a /RAS signal falls, a row address signal is accepted into address buffer 105 and then input to row decoder 102. Then, at a time point at which a /CAS signal falls, a column address signal is accepted into address buffer 105 and then input to column decoder 103. At this time, if a /WE signal is held at a logic high level (or an H level), the following series of reading operations are carried out. That is, storage data of a location of a designated row and column are amplified and then transferred to the data output buffer. With an output enable signal (a /OE signal) attaining a logic low level (or an L level), data are output to an output pin.
Similarly, a writing operation will now be described by reference to FIG. 14.
An operation in which a row address and a column address are accepted into address buffer 105 is the same as the one carried out during the reading operation. In the writing operation, however, at a time point at which a /CAS signal falls, the column address is accepted into buffer 105 and data D.sub.in (input data) are accepted into data input buffer 106. The accepted data are written on bit lines selected by the column address via an IO line from data input buffer 106. This writing operation is started when both signals/CAS and/WE attain a logic low level. In this case, the level of a/OE signal does not affect a series of operations.
FIG. 15 is an enlarged view of one memory cell MC constituting a memory cell array 101 of FIG. 12 and its peripheral circuits. A description will now be given on internal power supply voltages int. V.sub.CC, V.sub.CP, V.sub.BL and V.sub.BB with reference to FIG. 15.
A consideration will be given on a case where a logic high level is stored in a memory capacitor Cs by way of example. A description will be given on an operation for reading this stored information from memory cell MC. FIG. 16 shows time variations of the level of signals at various parts of FIG. 15.
A reference potential V.sub.CP of the memory cell capacitor is biased to a potential V.sub.CP (=V.sub.CC /2) formed in a cell plate voltage generation circuit 111 of FIG. 12, at an arbitrary time.
Further, a p well having an n channel MOS transistor formed therein is biased to a negative potential V.sub.BB (approximately -2 V to -3 V) formed in a substrate bias generation circuit 113 of FIG. 12.
At a time t.sub.0 in a standby state, since a signal of a logic high level is stored in the memory cell capacitor, a potential of its counter electrode (a storage node) is V.sub.CC. At this time, a potential of a word line (WL) is at a logic low level, a transistor Q51 is OFF, and memory cell capacitor Cs is in an electrical floating state for bit lines.
On the other hand, a potential of bit lines (BL and /BL) is held at a potential V.sub.BL (normally V.sub.CC /2) formed in a bit line precharge voltage generation circuit 112 of FIG. 12 since a bit line equalize signal (a BLEQ signal) is at a logic high level and transistors Q52, Q53 and Q54 are ON.
Then, at a time t.sub.1, the BLEQ signal attains a logic low level, transistors Q52, Q53 and Q54 are turned off, and the bit line pair BL and/BL is put in an electrical floating state.
At a time t.sub.2, when the potential of the word line (WL) attains a logic high level, transistor Q51 is turned on, charges stored in memory capacitor Cs are injected into the bit line BL, so that the potential of the bit line BL rises against the bit line /BL. The potential difference made here is, however, only a slight variation of several hundreds mV in general.
At a time t.sub.3, the sense amplifier starts its operation in response to its activation signal (not shown), amplifies the above slight potential difference, raises the potential of the bit line BL up to V.sub.CC and drops the potential of the bit line /BL down to 0. This potential difference V.sub.CC is externally derived as an output signal.
At a time t.sub.5, the potential of the word line attains a logic low level and transistor Q51 is turned off, so that the potential of the storage node is again held at the potential V.sub.CC (a logic high level) which is formed prior to reading.
At a time t.sub.6, the BLEQ signal attains a logic high level, and bit lines BL and /BL are precharged to V.sub.BL again.
As described above, since reading of storage information from memory cells is carried out by amplification of small voltages, stability of internal power supply voltages is necessary in order to maintain S/N ratios, and a sufficient operating margin for variations of values of the voltages is also indispensable.
Moreover, normal reading and writing operations of the above described DRAM have the following two features.
One feature is that since internal power supply voltages int. V.sub.CC, V.sub.CP, V.sub.BL , V.sub.BB and the like are uniquely set to a definite value once external power supply voltage ext. V.sub.CC is determined, it is impossible to externally measure the set value of internal power supply voltages or directly change the set value independently.
The other feature is that even if the /OE signal per se has its internal value int. OE always held at a logic high level, that is, the /OE signal is held at a logic low level, normal reading and writing operations are available.
In order to enable exact evaluations of operating margins for internal power supply voltages, a semiconductor integrated circuit apparatus disclosed in, e.g., Japanese Patent Laying-Open No. 3-160699 has attempted to resolve the problem of the above described first feature. A description will now be made on a configuration and a function of the disclosed embodiment.
FIG. 17 shows a circuit configuration of an internal voltage lowering circuit shown in the above embodiment.
A voltage down converter VD basically includes a differential amplifier circuit comprised of MOSFETs Q11, Q12 and Q13 employing as loads a current mirror circuit comprised of MOSFETs Q1 and Q2.
MOSFETs Q11 and Q12 have their gates being an inversion input terminal and a noninversion input terminal, respectively, and MOSFET Q13 has its gate and its drain coupled in common, acting as a constant current power source. MOSFET Q11 has its gate supplied with a reference voltage V.sub.REF, and drains of MOSFETs Q1 and Q11 which are coupled in common are further coupled to a gate of a p channel MOSFET Q3. MOSFET Q3 has its source coupled to a power supply voltage ext. V.sub.CC and its drain coupled to the gate of MOSFET Q12 and also to an internal power supply voltage supply point int. V.sub.CC.
If the level of internal power supply voltage int. V.sub.CC rises higher than a reference potential V.sub.REF, for example, conductance of MOSFET Q12 increases, while conductance of MOSFET Q11 decreases. Accordingly, a gate voltage of MOSFET Q3 becomes higher and its conductance becomes smaller, resulting in the lower level of internal power supply voltage int. V.sub.CC. Conversely, if the level of internal power supply voltage int. V.sub.CC falls lower than reference potential V.sub.REF, the circuit operates to make the level of int. V.sub.CC higher oppositely to the above case. In such a manner, the level of int. V.sub.CC is converged to and made stable at reference potential V.sub.REF.
A reference voltage generation circuit VrG is a circuit for applying an internal reference potential V.sub.r 1 to the above described voltage lowering circuit VD.
A switch circuit SC is a switching circuit for applying reference potential V.sub.r 1 to voltage lowering circuit VD when a test mode signal t.sub.e applied from a signal source not shown is at a logic low level, and for connecting a reference potential input terminal of voltage lower circuit VD and an external terminal A0 when test mode signal t.sub.e is at a logic high level. FIG. 17 shows such a configuration that both transistors Q14 and Q15 are n channel MOSFETs, and transistors Q14 has its gate supplied with an inversion signal of test mode signal t.sub.e, by an inverter N1.
Therefore, the above described internal voltage lowering circuit VD provides a method of controlling internal power supply voltage int. V.sub.CC in response to test mode signal t.sub.e during testing by applying an arbitrary reference potential V.sub.r 2 from external terminal A0.
However, the above described variable internal power supply circuit controlled by the external terminal potential has the following three problems.
The first problem is that there is not provided a method of measuring, during actual operations, potentials applied by the internal power supply circuit to a semiconductor integrated circuit incorporating the internal power supply circuit. A circuit structure enabling the above method is first desirable in order to make analysis of circuit operations and enhance stability and reliability of integrated circuit operations.
The second problem is that no protection is made against overshooting of external terminal potentials to positive values or undershooting of the potentials to negative values which inevitably occur during testing by the external terminal.
If the above described overshooting or undershooting generated at the external terminal is transmitted directly to internal circuits, this leads to destruction of internal storage information or damages and the like of elements in the worst case in, for example, a DRAM.
The third problem is that in the case where internal generation potentials sometimes generate negative potentials such as substrate bias potential V.sub.BB as described above, a countermeasure for the above described undershooting to negative values should be extended to more negative potentials.